The present invention relates generally to integrated circuit memory devices and, more particularly, to a high performance, domino Static Random Access Memory (SRAM) in which the core cells of the memory are segmented into subarrays accessed by local bit lines connected to global bit lines, with an interface between dual read and write global bit line pairs and local bit line pairs.
As will be appreciated by those skilled in the art, in a domino SRAM, the individual cells do not employ sense amplifiers to sense the differential voltage on the bit line pairs coupled to the cross-coupled inverters that store the data. Rather, for a domino SRAM, the local bit line is precharged, discharged, and the discharge is detected. The local bit line, the means to precharge the local bit line, and the detector define a dynamic node of the domino SRAM. More detailed information regarding the construction and operation of domino SRAMs may be found in U.S. Pat. Nos. 5,729,501 and 6,657,886, both assigned to the assignee of this application, and incorporated herein by reference.
In addition, U.S. Pat. No. 6,058,065, also assigned to the assignee of this application and incorporated herein by reference, discloses a memory array in which the core cells are organized in subarrays accessed by local bit lines connected to global bit lines. U.S. Pat. No. 7,113,433, also assigned to the assignee of this application and incorporated herein by reference, discloses a domino SRAM with one pair of global bit lines for a read operation and another pair of global bit lines for a write operation. An advantage of having two global bit line pairs is better overall performance in terms of faster reading from and writing to the memory cells. However, it is important that the interface from the global bit lines to the local bit line pairs does not detract from these performance gains.